fn7113 rev 2.00 page 1 of 7 july 6, 2006 fn7113 rev 2.00 july 6, 2006 el7104 high speed, single channel, power mosfet driver datasheet the el7104 is a mat ched driver ic that improves the operation of the industry-standa rd tc-4420/29 clock drivers. the elantec version is a very h igh speed driver capable of delivering peak currents of 1a into highly capacitive loads. the high speed performance is achieved by means of a proprietary turbo-driver circui t that speeds up input stages by tapping the wider voltage swing at the o utput. improved speed and drive capability are enhanced by matched rise and fall delay times. these ma tched delays maintain the integrity of input-to-output pu lse-widths to reduce timing errors and clock skew problems. this improved performance is accompanied by a 10-fold r eduction in supply currents over bipolar drivers, yet without the delay time problems commonly associated with cmos drivers. the el7104 is available in 8 -pin so and 8-pin pdip packages and is specified for operation over the full -40c to +85c temperature range. features ? industry-standard driver replacement ? improved response times ? matched rise and fall times ? reduced clock skew ? low output impedance ? low input capacitance ? high noise immunity ? improved clocking rate ? low supply current ? wide operating range ? separate drain connections ? pb-free available (rohs compliant) applications ? clock/line drivers ? ccd drivers ? ultrasound transducer drivers ? power mosfet drivers ? switch mode power supplies ? resonant charging ? cascoded drivers pinout el7104 (8-pin so, pdip) top view ordering information part number part marking package tape & reel pkg. dwg. # el7104cn el7104cn 8 ld pdip - mdp0031 EL7104CNZ el7104cn z 8 ld pdip* - mdp0031 el7104cs 7104cs 8 ld soic - mdp0027 el7104cs-t7 7104cs 8 ld soic 7 mdp0027 el7104cs-t13 7104cs 8 ld soic 13 mdp0027 el7104csz (see note) 7104csz 8 ld soic (pb-free) - mdp0027 el7104csz-t7 (see note) 7104csz 8 ld soic (pb-free) 7 mdp0027 el7104csz-t13 (see note) 7104csz 8 ld soic (pb-free) 13 mdp0027 note: intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatib le with both snpb and pb-free soldering operations. intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *pb-free pdips can be used for through hole wave solder process ing only. they are not intended for use in reflow solder processing applications. 1 2 3 4 8 7 6 5 v+ in nc gnd v+ p_out n_out gnd
el7104 fn7113 rev 2.00 page 2 of 7 july 6, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = 25c) supply (v+ to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5v input pins . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to +0.3v above v+ peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4a ambient operating temperature . . . . . . . . . . . . . . . .-4 0c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-6 5c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c power dissipation so . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mw pdip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mw caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc electrical specifications v+ = 15v, t a = 25c unless otherwise specified. parameter description conditions min typ max unit input v ih logic 1 input voltage 2.4 v i ih logic 1 input current @v+ 0.1 10 a v il logic 0 input voltage 0.8 v i il logic 0 input current @0v 0.1 10 a v hvs input hysteresis 0.3 v output r oh pull-up resistance i out = -100ma 1.5 4 ? r ol pull-down resistance i out = +100ma 2 4 ? i out output leakage current v+/gnd 0.2 10 a i pk peak output current source/sink 4.0 a i dc continuous output current source/sink 200 ma power supply i s power supply current input = v+ 4.5 7.5 ma v s operating voltage 4.5 16 v ac electrical specifications v = 15v, t a = 25c unless otherwise specified. parameter description conditions min typ max unit switching characteristics (v dd = v h = 12v; v l = -3v) t r rise time c l = 1000pf 7.5 ns c l = 2000pf 10 20 ns t f fall time c l = 1000pf 10 ns c l = 2000pf 15 20 ns t d-on turn-on delay time see timing table 18 25 ns t d-off turn-off delay time see timing table 18 25 ns
el7104 fn7113 rev 2.00 page 3 of 7 july 6, 2006 timing table standard test configuration simplified schematic 5v 2.5v 90% 10% 90% 10% 0 t d1 t d2 t f t r t r t f inverted output el7114 non-inverted output el7104 input 18 2 45 6 7 d.u.t. input signal output signal 4.7f 2000pf
el7104 fn7113 rev 2.00 page 4 of 7 july 6, 2006 typical performance curves max power/derating curves switch threshold vs supply voltage peak drive vs supply voltage input current vs voltage quiescent supply current on resistance vs supply voltage
el7104 fn7113 rev 2.00 page 5 of 7 july 6, 2006 typical performance curves (continued) average supply current vs voltage and frequency rise/fall time vs load rise/fall time vs supply voltage propagation delay vs supply voltage rise/fall time vs temperature rise/fall time vs temperature
el7104 fn7113 rev 2.00 page 6 of 7 july 6, 2006 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail x c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150) so16 (0.300) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ? 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ? 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ? 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ? 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ? 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ? 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ? 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ? 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
fn7113 rev 2.00 page 7 of 7 july 6, 2006 el7104 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2003-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol pdip8 pdip14 pdip16 pdip18 pdip20 tolerance notes a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. b 2/99 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the leads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
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